Exemplary embodiments of the present invention relate to a protection circuit for a semiconductor device, and more particularly, to a protection circuit for preventing an electrical effect of charges caused by plasma induced damage occurring during a fabrication process of a MOS transistor.
The reliability of semiconductor devices is influenced by fabrication processes of the semiconductor devices. In particular, processes using plasma charges have a greater influence on the reliability of semiconductor devices.
In recent fabrication processes of semiconductor devices, a plasma process is used more often in order to form a plurality of metal layers. Hence, during the plasma process, gate electrode oxide layers and metal interconnections of the semiconductor devices may be severely damaged by plasma charges.
Specifically, charges generated during the plasma process are accumulated in a P-type well of a substrate. When bias power is applied to the P-type well, the charges accumulated in the P-type well are discharged through metal interconnections at the same time. Therefore, the metal interconnections may be melted or the gate electrode oxide layers may be damaged.
To address those concerns, a conventional semiconductor device further includes a protection diode which is capable of discharging charges accumulated in a P-type well.
FIG. 1 is a circuit diagram illustrating a conventional protection circuit and a conventional semiconductor device.
Referring to FIG. 1, a diode is provided as an example of a protection circuit 100, and an inverter is provided as an example of a semiconductor device 200.
The semiconductor device 200 includes a PMOS transistor PM1 and an NMOS transistor NM1 each having a source, a drain, and a gate electrode.
In the configuration of the semiconductor device 200, a power supply voltage VDD is applied to the source of the PMOS transistor PM1, and a ground voltage VSS is applied to the source of the NMOS transistor NM1. The gate electrode of the PMOS transistor PM1 and the gate electrode of the NMOS transistor NM1 are commonly coupled to an input terminal IN, and the drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are commonly coupled to an output terminal OUT, thereby constituting an inverter. Thus, the inverter inverts a signal inputted through the input terminal IN and outputs the inverted signal through the output terminal OUT.
The diode included in the protection circuit 100 is coupled between the input terminal IN and the semiconductor device 200. When charges are accumulated in a P-type well P-WELL and generate a voltage level greater than a threshold voltage level of the diode (for example, approximately 0.7 V), the diode discharges the accumulated charges through the input terminal IN.
FIG. 2 is a cross-sectional view illustrating the configuration of the protection circuit 100 and the semiconductor device 200 of FIG. 1.
The semiconductor device 200 includes the PMOS transistor PM1 and the NMOS transistor NM1, and the protection circuit 100 includes the diode.
The NMOS transistor NM1 includes a gate electrode oxide layer 20, a gate electrode 30, spacers 40A and 40B, a source 50A, and a drain 50B. The gate electrode oxide layer 20 is formed on a P-type well P-WELL which is formed by doping P-type impurities into a silicon substrate. The gate electrode 30 is formed on the gate electrode oxide layer 20. The spacers 40A and 40B are formed on both sidewalls of the gate electrode 30. The source 50A and the drain 50B are formed by doping N-type impurities into the P-type well P-WELL.
The PMOS transistor PM1 includes a gate electrode oxide layer 60, a gate electrode 70, spacers 80A and SOB, a drain 90A, and a source 90B. The gate electrode oxide layer 60 is formed on an N-type well N-WELL which is formed by doping N-type impurities into the silicon substrate. The gate electrode 70 is formed on the gate electrode oxide layer 60. The spacers 80A and 80B are formed on both sidewalls of the gate electrode 70. The drain 90A and the source 90B are formed by doping P-type impurities into the N-type well N-WELL.
The diode is formed by doping N-type impurities into the P-type well P-WELL between the PMOS transistor PM1 and the NMOS transistor NM1.
At this time, the gate electrode 30 of the NMOS transistor NM1, the gate electrode 70 of the PMOS transistor PM1, and the diode are coupled to the input terminal IN through a metal interconnection.
When the potential of the charges accumulated in the P-type well P-WELL is higher than that of the threshold voltage level (approximately 0.7 V), the diode discharges the accumulated charges through the input terminal IN, thereby protecting the semiconductor device.
However, since an amount of charges which can be discharged to the input terminal IN by the diode is limited, a plurality of diodes is required in order to serve as the protection circuit. This may cause difficulties in the fabrication processes and the circuit design of the semiconductor device. Furthermore, since a plurality of diodes is to be disposed in the protection circuit, a circuit area for the protection circuit increases. Thus, the protection circuit including a plurality of diodes may be seen as inefficient in view of the design of the semiconductor device.